In the classical multiplier architecture, the multiplier operand and the multiplicand operand are input to partial product generators. For example, if each operand is eight binary bits long, then eight partial products will be produced by the partial product generators. The partial products must then be added to produce the final product in the multiplier. Prior art multiplier designs use conventional carry save adders in an arrangement such as is shown in FIG. 1 for the addition of a single binary bit position for eight partial products. There can be as many as 16 single bit columns such as that shown in FIG. 1, required to complete the necessary additions of the partial products in an eight by eight multiplier. The term carry save adder is used herein to refer to a one bit logic block which adds an augend bit, an addend bit, and a carry bit and produces a resultant sum bit and carry bit. The one bit carry save adders A1', A2', A3', A4', A5', A6' and A7' in FIG. 1 employ the classical approach to forming the sum as is shown in equation 1a and to form the carry bit as is shown in equation 3. As is seen in equations 1a and 3, only true values for the sums and carries are produced and propagated from one level of carry save adders to the next. For example, as is shown for bit column N in FIG. 1, the adder A4' receives a true sum S11 from the adder A1', a true sum S21 from the adder A2', and a true sum S31 from the adder A3'. Those three sums are added in the adder A4' to produce a true sum S41 and a true carry C41.
A conventional carry save adder such as A4' in FIG. 1 has a sum generation circuit as shown in FIG. 4, which generates a true sum by applying the first two operands, for example A and B to a first exclusive OR circuit 23 and then the output of that first exclusive OR circuit is applied as a first input to a second exclusive OR circuit 30, the other input to the second exclusive OR circuit being the third operand C. The output of the second exclusive OR circuit is then the sum. This operation requires two delay intervals to accomplish. The operands A, B and C in FIG. 4 correspond to the operands S11, S21 and S31 for the adder A4' in FIG. 1.
The carry generation operation for a conventional carry save adder such as A4' in FIG. 1 would apply the three operand inputs S11, S21 and S31 in respective pairs to each of three AND gates, the outputs of which are OR'ed together to provide the true carry output C41. This operation also requires two logic delay intervals to accomplish. Even if the sum and carry operations were to be performed in parallel, the two gate delay limitation is the minimum time required for each carry save adder stage in the multiplier of FIG. 1 to complete generating a true valued carry. Since multipliers generally have four or more carry save adder stages to carry out the addition of the partial products, this limitation in the amount of delay required to generate sum bits and carry bits imposes a significant overall limitation in the multiplier operation.